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138
8024A–AVR–04/08
ATmega8HVA/16HVA
24.4
Register Description
24.4.1
FCSR – FET Control and Status Register
Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega8HVA/16HVA, and will always read as zero.
Bit 3 – DUVRD: Deep Under-voltage Recovery Disabled
When the DUVRD is cleared (zero), the FET Driver will be forced to operate in Deep Under-volt-
age Recovery DUVR mode. See ”DUVR – Deep Under-Voltage Recovery Mode operation” on
page 137 for details. To avoid that the FET driver tries to switch on the C-FET during current
protection or during internal reset, the DUVRD bit is overridden to one by hardware in these
cases. When this bit is set (one), Deep Under-voltage Recovery mode of the FET Driver will be
disabled.
Bit 2 – CPS: Current Protection Status
The CPS bit shows the status of the Current Protection. This bit is set (one) when a Current Pro-
tection is active, and cleared (zero) otherwise.
Bit 1 – DFE: Discharge FET Enable
When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of
the Battery Protection circuitry. When this bit is set (one), the Discharge FET is enabled. This bit
will automatically be cleared by the CBP circuitry when Current Protection is activated. When
this bit is cleared, Short-circuit, Discharge High-current and Discharge Over-current are disabled
regardless of the settings in the BPCR Register.
Bit 0 – CFE: Charge FET Enable
When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of
the Battery Protection circuitry. When this bit is set (one), the Charge FET is enabled. This bit
will automatically be cleared by the CBP circuitry when Current Protection is activated. When
this bit is cleared and the DUVRD bit is set, Charge High-current Protection and Charge Over-
current Protection are disabled regardless of the settings in the BPCR Register. When the
DUVRD bit is cleared, the charge FET will be enabled by DUVR mode regardless of the CFE
status.
Note:
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the FCSR register is written. Any writ-
ing to the FCSR register during this period will be ignored.
Bit
765
4
3
2
1
0
(0xF0)
–
DUVRD
CPS
DFE
CFE
FCSR
Read/Write
R
R/W
R
R/W
Initial Value
0
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